Vitis 2021.1 Embedded Platform for Zybo-Z7–20The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7–20 board from Digilent.Aug 15, 2021Aug 15, 2021
How to Reduce II in HLS: Part 4This week’s problem is the traditional matrix-vector multiplication kernel used in several applications such as machine learning and image…May 24, 2021May 24, 2021
“Logic System Design with High-Level Synthesis": an Introductory Course for UndergraduateThis article introduces an introductory course on high-level synthetisis (HLS) that is suitable for undergraduate students and software or…Apr 15, 2021Apr 15, 2021
UART Transmit with HLS for FPGALike my previous projects, this one also demonstrates that “Designing digital systems with HLS for FPGA is fun”. If you are interested in…Oct 26, 2020Oct 26, 2020
A 0–9 Up/Down Counter in HLSGoal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing digital…Oct 2, 2020Oct 2, 2020
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: PortsIn this blog, I am going to explain how to write our first accelerator using the Xilinx Vitis unified platform. The algorithm is a simple…Dec 2, 2019Dec 2, 2019
Fundamentals of High-Level Synthesis — Part 4: Dependency, Concurrency and parallelism“At the bottom of every person’s dependency, there is always pain, Discovering the pain and healing it is an essential step in ending…Nov 18, 2019Nov 18, 2019
Embedded Hardware Accelerator with Xilinx Vitis: Part 2: Create a Linux-based PlatformIn the previous blog, I briefly explained the concept of platform-based design in the context of embedded FPGA. And the problems that it…Nov 15, 2019Nov 15, 2019
