Like my previous projects, this one also demonstrates that “Designing digital systems with HLS for FPGA is fun”. If you are interested in learning HLS coding techniques please refer here or here.

UART is an old mechanism for serial communication which still is used in several electronic boards and computing platforms. Its implementation in an HDL language is not tricky and can be considered as an undergraduate homework. Here, I am going to take this example and show how easy and fun it is to implement that in HLS.

So, conceptually it is a trivial project; however, it is instructive…

Goal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing digital systems.

If you are interested in designing with HLS please have a look at
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

Project description: In this project, I am going to design a 0–9 Up/Down counter with initialisation signal. Figure 1 shows an overview of the project.

Abstract:

Describing a combinational task in HLS is very important as it has a direct impact on the whole system performance. Here, taking a simple example, I will explain this matter. If you would like to know how to design combinational circuits in HLS, please refer to “ Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits “.

Introduction

A high-level synthesis tool converts an algorithm to an equivalent RTL description. This description represents a logic circuit, which can be implemented by the ASIC or FPGA technologies.

A logic circuit can be one of the two types: combinational or sequential…

Traditionally, FPGA was meant to be used by hardware engineers. And only designers with great hardware knowledge could use them. These designers should use one of the hardware description languages (HDL) such as VHDL or Verilog and should follow a cycle-accurate design methodology. This approach makes debugging and verification very difficult and time-consuming. Therefore, several unique FPGA properties, such as low power consumption, high-performance, and small footprint, could only be harnessed by a limited group of engineers.

To address this issue, researchers have proposed high-level synthesis (HLS) techniques and tools. HLS makes FPGAs accessible to software engineers. The main goal…

In this blog, I am going to explain how to write our first accelerator using the Xilinx Vitis unified platform. The algorithm is a simple version of the famous sgemv function from BLAS specification. You can extend that later to cover all the cases for this function.

The sgemv function implements the matrix-vector multiplication operator. The following equation describes this function that we are going to implement in hardware.

In the last two blogs, I explicitly talked about concurrency and parallelism. I also mentioned about dependency. However, the dependency concept and its relation to concurrency and parallelism need more discussion. Here, I am going to talk about this relationship.

Maximising parallelism is our ultimate goal in accelerating an algorithm using FPGA. This goal is achievable, mainly due to the abundant computational and memory resources available. However, utilising parallelism is not easily accessible if enough concurrency doesn’t exist in the task description. As I mentioned in the previous post, one way of describing the concurrency in the code is using…

In the previous blog in this series, I briefly explained the concept of platform-based design in the context of embedded FPGA. And the problems that it is going to address. In this blog, I go through different parts of the Xilinx Vitis system platform. The platform encapsulates the hardware details, the Linux operating system kernel. It also contains the Xilinx runtime system and related libraries.

In the previous blog, I explained the difference between concurrency and parallelism concepts in high-level synthesis. Whereas the concurrency is a concept at the algorithmic or functional level, the parallelism is a realisation of the concurrency at the hardware level. Software programmers employ compiler tools to transform the algorithmic description into a representation suitable for hardware. Accordingly, in high-synthesis context, the role of HLS compiler is transforming the concurrency to parallelism to maximise the efficiency which can be throughput, latency, energy consumption among others. Therefore, the parallelism brings the performance and concurrency enables the parallelism exploitation. If designers cannot describe…