Aug 15, 2021Vitis 2021.1 Embedded Platform for Zybo-Z7–20The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7–20 board from Digilent. If you are interested to know how to use this platform to accelerate different compute-intensive tasks such as Support Vector Machine (SVM) on an FPGA-based embedded system, please refer to…Fpga8 min read
May 24, 2021How to Reduce II in HLS: Part 4This week’s problem is the traditional matrix-vector multiplication kernel used in several applications such as machine learning and image processing. This figure shows the software-oriented code that describes the kernel. The code consists of a two-level loop nest that reads the matrix A and vector and generates the output elements…Fpga1 min read
Apr 15, 2021“Logic System Design with High-Level Synthesis": an Introductory Course for UndergraduateThis article introduces an introductory course on high-level synthesis (HLS) that is suitable for undergraduate students and software or hardware designers with minimum logic design knowledge. The course covers the design of all traditional circuits explained in an HDL-based logic system design course. Currently the course has two parts that…Fpga Design3 min read
Oct 26, 2020UART Transmit with HLS for FPGALike my previous projects, this one also demonstrates that “Designing digital systems with HLS for FPGA is fun”. If you are interested in learning HLS coding techniques please refer here or here. UART is an old mechanism for serial communication which still is used in several electronic boards and computing…Fpga3 min read
Oct 2, 2020A 0–9 Up/Down Counter in HLSGoal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing digital systems. If you are interested in designing with HLS please have a look at Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Project description: In this project…Fpga8 min read
Sep 29, 2020The Importance of Combinational Circuits in HLSAbstract: Describing a combinational task in HLS is very important as it has a direct impact on the whole system performance. Here, taking a simple example, I will explain this matter. …High Level Synthesis5 min read
Dec 21, 2019Embedded System HLS with Vitis: Communication with SoftwareTraditionally, FPGA was meant to be used by hardware engineers. And only designers with great hardware knowledge could use them. These designers should use one of the hardware description languages (HDL) such as VHDL or Verilog and should follow a cycle-accurate design methodology. This approach makes debugging and verification very…Programming6 min read
Dec 2, 2019Embedded Hardware Accelerator with Xilinx Vitis: Part 4: PortsIn this blog, I am going to explain how to write our first accelerator using the Xilinx Vitis unified platform. The algorithm is a simple version of the famous sgemv function from BLAS specification. You can extend that later to cover all the cases for this function. The sgemv function…High Level Synthesis5 min read
Nov 18, 2019Fundamentals of High-Level Synthesis — Part 4: Dependency, Concurrency and parallelismIn the last two blogs, I explicitly talked about concurrency and parallelism. I also mentioned about dependency. However, the dependency concept and its relation to concurrency and parallelism need more discussion. Here, I am going to talk about this relationship. Maximising parallelism is our ultimate goal in accelerating an algorithm…Programming4 min read
Nov 15, 2019Embedded Hardware Accelerator with Xilinx Vitis: Part 2: Create a Linux-based PlatformIn the previous blog in this series, I briefly explained the concept of platform-based design in the context of embedded FPGA. And the problems that it is going to address. In this blog, I go through different parts of the Xilinx Vitis system platform. The platform encapsulates the hardware details…Accelerator2 min read
