A 0–9 Up/Down Counter in HLS

Goal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing digital systems.

If you are interested in designing with HLS please have a look at
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

Project description: In this project, I am going to design a 0–9 Up/Down counter with initialisation signal. Figure 1 shows an overview of the project.

For implementing this project, I am using the Xilinx HLS platform provided by Vivado Design Suite — HLx Editions. Also, I will use the Basys 3 Evaluation board as the target FPGA platform. Figure 2 shows the layout of the final up/down counter on the board. The right-hand side 7-segment shows the counter. The UP push-button is used for up counting, and the DOWN push-button is used for the down counting. INIT push-button initialises the counter. Four slide switches denoted by “INIT value” will be used for entering the initialisation number. Also, four LEDs show this value.