A 0–9 Up/Down Counter in HLS
8 min readOct 2, 2020
Goal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing digital systems.
If you are interested in designing with HLS please have a look at
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits
Project description: In this project, I am going to design a 0–9 Up/Down counter with…
