Embedded System HLS with Vitis: Communication with Software

Traditionally, FPGA was meant to be used by hardware engineers. And only designers with great hardware knowledge could use them. These designers should use one of the hardware description languages (HDL) such as VHDL or Verilog and should follow a cycle-accurate design methodology. This approach makes debugging and verification very difficult and time-consuming. Therefore, several unique FPGA properties, such as low power consumption, high-performance, and small footprint, could only be harnessed by a limited group of engineers.

To address this issue, researchers have proposed high-level synthesis (HLS) techniques and tools. HLS makes FPGAs accessible to software engineers. The main goal of HLS is directly mapping a high-level function described (usually in C/C++) on an FPGA. Therefore, designers with little or no hardware knowledge will be able to use an FPGA to run a given algorithm. Several HLS platforms have been proposed by industry and academia that have fairly managed to achieve this goal. The Xilinx Vitis unified software platform is one of the widely adopted toolsets and techniques that targeted FPGA hardware. In this blog, I will consider this platform to explain some basic ideas in HLS.

A typical HLS tool converts an algorithm, described in C/C++ without any timing information, into the equivalent…