“Logic System Design with High-Level Synthesis": an Introductory Course for Undergraduate

This article introduces an introductory course on high-level synthesis (HLS) that is suitable for undergraduate students and software or hardware designers with minimum logic design knowledge. The course covers the design of all traditional circuits explained in an HDL-based logic system design course. Currently the course has two parts that contain 17 hours on-demand videos and more than 300 downloadable resources including quizzes, exercises solutions and their source and testbench codes in HLS. For accessing the course series please refer here.

High-level synthesis (HLS) is becoming a must-have skill for FPGA-based embedded system designers. Several industrial and academic tools are available that synthesise an algorithm described in a high-level language such as C/C++. This shows that HLS tools can convert a C code into the corresponding logic design. However, there is no systematic design methodology to describe a logic circuit in HLS. Whereas HDL languages such as VHDL and Verilog have been accepted as the industrial standard for describing logic systems, the HLS is not used widely by the industry as the description language for logic systems. There are several reasons for that
1- The hardware resulted from HLS is not efficient
2- There is not any systematic methodology that describes all…